There are a number of different types of semiconductor packages. One type of semiconductor package is called a flip chip in a leaded molded package (FLMP). This package is described in detail in U.S. patent application Ser. No. 09/464,885, entitled “Flip Chip in Molded Lead Package & Method of Manufacture Thereof”, by Rajeev Joshi, filed on Dec. 16, 1999. The flip chip in a leaded molded package includes a leadframe structure that has a die attach pad and leads that extend away from the die attach pad. The die attach pad is coupled to the front side of a semiconductor die with solder. A molding material covers the die attach pad and the front side of the semiconductor die, while the back side of the semiconductor die is exposed through the molding material. The leads extend laterally away from the molding material and are substantially co-planar with the back side of the semiconductor die and a surface of the molding material. The front side of the semiconductor die may correspond to the gate region and the source region of a MOSFET (metal oxide semiconductor field effect transistor) in the semiconductor die. The back side of the semiconductor die may correspond to the drain region of the MOSFET. When the semiconductor package is mounted to a circuit substrate, the back side of the die and the leads are connected to conductive lands on the circuit substrate with solder. The circuit substrate may be a printed circuit board.
The above-described semiconductor package has a number of advantages. First, because there is a substantially direct electrical connection between the back side of the semiconductor die and the circuit substrate, and because there are short, low-resistance conductive paths between the source and gate regions in the semiconductor die, and the circuit substrate, the die package resistance is nearly eliminated, allowing for the industry's lowest RDS(ON) for the same package footprint. RDS(ON) is the on-resistance that is associated with turning a MOSFET in the die package on from an off-state. Second, the above-described semiconductor package is thin. For example, compared to a conventional wire bonded SOIC-8 package, which is about 1.6 mm tall, a flip chip in a leaded molded package can have a height of less than about 1.0 mm. The flip chip in a leaded molded package can have the same or better electrical and thermal performance, while being smaller than a standard SOIC-8 package. Thin semiconductor packages are especially desirable for small portable electronic devices such as wireless phones and laptop computers.
While the above-described semiconductor package has a number of advantages, a number of improvements could be made. When mass producing semiconductor packages of the type described above, a number of problems can occur. The problems include, for example, silicon cracks that form because of an uneven die standoff from the die attach region of the leadframe structure, moisture seepage into the semiconductor package, delamination between the leadframe structure and the molding material, and molding material bleed on an exposed die surface and leads (which can hinder the package from functioning efficiently or potentially fail during device applications). Other problems include poor solder adhesion between the circuit board bonding pads and the semiconductor die and uneven cutting during the singulation process.
These and other problems are addressed by embodiments of the invention.